1. Technical Field
The present invention generally relates to display technology fields and, particularly to a gate driving circuit adapted for applying into active matrix display devices.
2. Description of the Related Art
Referring to FIG. 1, showing a schematic structural diagram of a conventional active matrix display device. As illustrated in FIG. 1, the active matrix display device 100 includes a display substrate 110, a printed circuit board 130, a plurality of source driver integrated circuits (not labeled) electrically coupled between the display substrate 110 and the printed circuit board 130, and a gate driving circuit including a plurality of cascade-connected gate driver integrated circuits Y1, Y2. The display substrate 110 has a thin film transistor array (not shown) formed thereon. The gate driver integrated circuits Y1, Y2 of the gate driving circuit are electrically coupled to the thin film transistor array of the display substrate 110 to switch the on/off states of thin film transistors in the thin film transistor array. The printed circuit board 130 has a pulse width modulation circuit 132 formed thereon. The pulse width modulation circuit 132 is subjected to the control of the control signal CS to modulate (e.g., angling modulate) the gate power supply voltage VGH and thereby a modulated voltage signal VGG is obtained. The modulated voltage signal VGG then is inputted into the gate driver integrated circuits Y1, Y2 of the gate driving circuit. Herein, the gate power supply voltage VGH is modulated by the pulse width modulation circuit 132, which facilitates a waveform of a gate signal during controlling the thin film transistors electrically coupled at the head of a gate line to be approximately the same as a waveform of the gate signal during controlling the thin film transistors electrically coupled at the tail of the gate line, and therefore even/uniform display effect can be achieved.
However, during the gate power supply voltage VGH is angling modulated to be the modulated voltage signal VGG, since the cascade-connected gate driving integrated circuits Y1, Y2 use the modulated voltage signal VGG provided by the same pulse width modulation circuit 132 as respective power supply voltages and further the potential of the modulated voltage signal VGG is periodically varied, when the potential of the modulated voltage signal VGG is firstly angled to a low level from the gate power supply voltage VGH and then retrieved to the gate power supply voltage VGH, a discharging current formed in the pulse width modulation circuit 132 will dramatically increase and thereby occur a high peak current, which would easily result in large power loss, even circuit burnout.